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US 2016/0239462 A1Published application
Multi-level hierarchical routing matrices for pattern-recognition processors
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown
Life of this patent
Estimating the term…
Abstract
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
Claims20
A device, comprising:
- a logical group comprising a plurality of route lines, a first feature cell, and a second feature cell, wherein the first feature cell is configured to transmit an output signal along a first route line of the plurality of route lines to the second feature cell as an input signal to the second feature cell, wherein the first feature cell and the second feature cell of the logical group are separate and distinct from any additional feature cells of any other logical group of the device.
A device comprising:
- a first logical group comprising a first plurality of route lines, a first feature cell, and a second feature cell, wherein the first feature cell is configured to transmit a first output signal along a first route line of the first plurality of route lines to the second feature cell as an input signal to the second feature cell;
- a second logical group comprising a second plurality of route lines, a third feature cell, and a fourth feature cell, wherein the third feature cell is configured to transmit a second output signal along a first route line of the second plurality of route lines to the fourth feature cell as an input signal to the fourth feature cell, wherein the first feature cell and the second feature cell of the first logical group are separate and distinct from the third feature cell and the fourth feature cell of the second logical group.
A system, comprising:
- a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of rows, wherein each row of the plurality of rows comprises a plurality of logical groups, wherein each logical group comprises:
- a plurality of route lines, a first feature cell, and a second feature cell, wherein a given feature cell of a given logical group is configured to transmit a state output signal from an enable output of the given feature cell to an enable input of another feature cell of the given group along a given route line, wherein the first feature cell and the second feature cell of each logical group of the plurality of logical groups are separate and distinct from feature cells of any other logical group of the plurality of logical groups.
Dependencies are inferred from the claim text.