Reconfigurable graph processor
AssigneeSynaptic Engines, LLC
InventorGautam Kavipurapu
Life of this patent
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Abstract
A graph processor has a planar matrix array of system resources. Resources in a same matrix or different planar matrices are interconnected through port blocks or global switched memories. Each port block includes a broadcast switch element and a receive switch element. The graph processor executes atomic execution paths that are generated from data flow graphs or computer programs by a scheduler. The scheduler linearizes resources and memories. The scheduler further maintains a linearized score board for tracking states of the resources.
Claims25
1-24. (canceled)
A graph processor comprising:
- i) a planar matrix array wherein the planar matrix array includes a set of planar matrices wherein each planar matrix includes a set of resources, wherein the set of resources are interconnected through port blocks and each resource of the set of resources is an atomic execution unit, wherein the atomic execution unit executes a single type of instruction;
- and
- ii) a switched memory wherein the switched memory includes port blocks for interconnecting the set of planar matrices.
A method for executing a set of computer program instructions on a graph processor, the method comprising:
- i) linearizing the state, type and coordinates of each resource in a planar matrix array of a graph processor into a linearized matrix array, wherein the planar matrix array includes a set of planar matrices wherein each planar matrix includes a set of resources, wherein each resource is an atomic execution unit, wherein the atomic execution unit executes a single type of instructions;
- ii) determining a flow graph corresponding to a set of computer program instructions;
- iii) linearizing a portion of the flow graph into a score board wherein the score board includes at least one node of the portion of the flow graph;
- iv) based on the linearized matrix array, mapping one node of the portion of the flow graph to an available resource of the planar matrix array;
- and
- v) the available resource executing the operation defined by the mapped node on the graph processor.
Dependencies are inferred from the claim text.