Efficient Calibration of a Low Power Parallel Data Communications Channel

A communications mechanism for communicating between digital data devices, comprising:

• a first plurality of parallel lines supporting a parallel communications link for communicating data in a first direction from a first digital data device to a second digital data device;
• a calibration mechanism for recalibrating said parallel communications link at each of a plurality of discrete times;
• wherein said calibration mechanism performs at least one calibration operation at each of said plurality of discrete times by temporarily suspending transmission of functional data on at least one line of said first plurality of parallel lines to perform the at least one calibration operation using the at least one line;
• and
• wherein, in at least one operating mode, the calibration mechanism selectively interrupts the at least one calibration operation to transmit functional data on the at least one line and resumes the at least one calibration operation at the conclusion of transmitting the functional data.

A digital data processing apparatus, comprising:

• a plurality of integrated circuit chips, said integrated circuit chips embodying at least an addressable main memory and at least one at least one programmable processor executing instructions storable in said addressable main memory;
• at least one parallel communications link, each said parallel communications link for communicating data between a respective pair of said plurality of integrated circuit chips, each said at least one parallel communications link having a respective plurality of parallel lines supporting data communication in a first direction from a first chip of the respective pair to a second chip of the respective pair;
• a respective calibration mechanism corresponding to each said parallel communications link for recalibrating the parallel communications link responsive to a respective externally generated command;
• a control program embodied as instructions executable on said at least one programmable processor and storable in said addressable main memory, said control program executing at least one software process which determines need for recalibration of said at least one parallel communications link based on at least one parameter other than a pre-determined schedule, and responsive to determining a need for recalibration of a link of said at least one parallel communications link, generates the respective externally generated command to the respective calibration mechanism to cause the respective calibration mechanism to recalibrate the link determined to have a need for recalibration.