Supporting flow control mechanism of bus between semiconductor dies assembled in wafer-level package
AssigneeMediatek Inc.
InventorYao-Chun Su
Life of this patent
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Abstract
A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.
Claims20
A semiconductor die assembled in a wafer-level package, comprising:
- a communication interface;
- and
- a bus master, coupled to a communication bus through the communication interface, wherein the bus master is arranged to communicate with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is further arranged to be controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.
A semiconductor die assembled in a wafer-level package, comprising:
- a communication interface;
- and
- a bus slave, coupled to a communication bus through the communication interface, wherein the bus slave is arranged to communicate with a bus master of another semiconductor die assembled in the wafer-level package via the communication bus, and is further arranged to trigger a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.
A wafer-level package comprising:
- a communication bus;
- and
- a semiconductor die, comprising:
- a plurality of bus masters, each arranged to be controlled by a flow control mechanism that manages a transaction flow over the communication bus;
- and
- a bus arbiter, arranged to perform arbitration upon transaction requests issued from the bus masters and grant an access right of the communication bus to only one of the bus masters at a time.
A wafer-level package comprising:
- a communication bus;
- and
- a semiconductor die, comprising:
- a plurality of bus slaves, each arranged to trigger a flow control mechanism that manages a transaction flow over the communication bus;
- and
- a bus dispatcher, arranged to dispatch the transaction flow from the communication bus to at least one of the bus slaves at a time.
Dependencies are inferred from the claim text.