Scheduling volatile memory maintenance events in a multi-processor system

A system for scheduling volatile memory maintenance events, the system comprising:

• means for determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface;
• means for providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event;
• means for each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event;
• and
• means for determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

A computer program embodied in a memory and executable by a processor for scheduling volatile memory maintenance events, the computer program comprising logic configured to:

• determine a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface;
• provide an interrupt signal to each of a plurality of processors on a system on chip (SoC);
• and
• determine when to execute the maintenance event in response to receiving one or more schedule notifications independently generated by the plurality of processors and based on a processor priority scheme.

A system for scheduling volatile memory maintenance events, the system comprising:

• a dynamic random access memory (DRAM) device;
• and
• a system on chip (SoC) comprising a plurality of processors and a DRAM controller electrically coupled to the DRAM device via a memory data interface, the DRAM controller comprising logic configured to:
• determine a time-of-service (ToS) window for executing a maintenance event for the DRAM device, the ToS window defined by a signal provided to each of the plurality of processors and a deadline for executing the maintenance event;
• and
• determine when to execute the maintenance event in response to receiving schedule notifications independently generated by the plurality of processors in response to the signal and based on a processor priority scheme.