High performance persistent memory for region-centric consistent and atomic updates

A system-on-a-chip (SoC) comprising:

• a two-level memory comprising a first level comprising a non-persistent cache, and a second level comprising a persistent memory, and
• a processor, operatively coupled to the two-level memory, comprising:
• a processing core to execute an application comprising instructions encoding a transaction with the persistent memory via the non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, wherein the cache line is associated with a cache line status, and
• a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

A method comprising:

• executing, by a processing core, an application comprising a transaction via a non-persistent cache to create a mapping from a virtual address space to a memory region associated with a memory region identifier (MRID) in the persistent memory;
• tagging a cache line of the non-persistent cache with the MRID, wherein the cache line is associated with a cache line status;
• detecting a failure event occurred associated with the memory region;
• determining a value of the cache line status;
• in response to determining the value of the cache line status indicating a committed state, evicting contents of the cache line to memory region;
• and
• in response to determining the value of the cache line status indicating an uncommitted state, discarding the contents of the cache line.