Faulty core recovery mechanisms for a three-dimensional network on a processor array

A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:

• presenting a test vector to a component of a processor array, wherein the component generates output in response to the test vector presented;
• making a first determination as to whether the component is faulty based on the output generated and an expected output;
• and
• based on the first determination, selectively signaling a switch of the processor array to bypass the component via at least one redundant data path of the processor array.

A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:

• presenting a test vector to a component of a processor array, wherein the component generates output in response to the test vector presented;
• making a first determination as to whether the component is faulty based on the output generated and an expected output;
• and
• based on the first determination, selectively signaling a switch of the processor array to bypass the component via at least one redundant data path of the processor array.