US 2016/0239304 A1 · METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS

Abstract

An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Claims6

Dependent claims

A system comprising:

a plurality of processors;
a processor interconnect to communicatively couple two of the plurality of processors;
and
a system memory comprising dynamic random access memory communicatively coupled to one or more of the plurality of processors over a memory interconnect;
one or more of the plurality of processors comprising:
a plurality of cores, one or more of the plurality of cores to concurrently execute multiple threads;
one or more of the plurality of cores to perform out-of-order execution of instructions of the threads;
one or more of the plurality of cores comprising:
instruction fetch logic to fetch instructions of one or more of the threads, instruction decode logic to decode the instructions,
register renaming logic to rename one or more registers within a register file, a data cache to cache data,
a translation lookaside buffer to store virtual to physical address translations,
a second level cache unit to cache instructions and data, and
an execution unit to execute a first instruction to abort transactional execution responsive to an abort condition.

10 more elements

Dependencies are inferred from the claim text.

Method, apparatus, and system for speculative abort control mechanisms

Life of this patent

Method, apparatus, and system for speculative abort control mechanisms

Life of this patent

Abstract

Claims6