Microprocessor using compressed and uncompressed microcode storage

A microprocessor comprising:

• a fetch unit operative to fetch architectural instructions from memory;
• an uncompressed microcode memory storage having M-bit wide addressable words;
• a compressed microcode memory storage having N-bit wide addressable words, where N<M;
• an instruction translator operative to receive the architectural instructions supplied by the fetch unit and translate them into microinstructions executable according to a microinstruction set architecture of the microprocessor;
• and
• an execution stage operative to receive microinstructions from the instruction translator and execute them;
• wherein when the instruction translator receives an architectural instruction, it:
• writes information identifying source and destination registers specified by the architectural instruction to an indirection register;
• issues one or more fetch addresses to retrieve a sequence of one or more microcode instructions from one of the uncompressed microcode memory storage and the compressed microcode memory storage to implement the architectural instruction;
• merges information in the indirection register with the sequence of one or more microcode instructions to generate a sequence of one or more implementing microinstructions.