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US 2016/0239299 A1Published application
System, apparatus, and method for improved efficiency of execution in signal processing algorithms
AssigneeIntel Corporation
InventorsChetan D. Hiremath, Udayan Murkherjee
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Abstract
Embodiments of methods, apparatuses, and machine-readable mediums for performing a bit reversal instruction in a computer processor are described. In some embodiments, the execution of such instruction causes the bit ordering for a source operand to be reversed and stored.
Claims24
A method of performing an instruction in a computer processor, comprising:
- fetching the instruction, wherein the instruction includes a source operand and a destination operand;
- decoding the fetched instruction;
- executing the decoded by reversing the bit ordering for the source operand such that a least significant bit becomes a most significant bit;
- storing a resulting bit-reversed data into the destination operand.
1 more element
A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
- fetching the instruction, wherein the instruction includes a source operand and a destination operand;
- decoding the fetched instruction;
- executing the decoded by reversing the bit ordering for the source operand such that a least significant bit becomes a most significant bit;
- storing a resulting bit-reversed data into the destination operand.
1 more element
An apparatus, comprising:
- an instruction fetch circuitry to fetch an instruction, wherein the instruction includes a source operand and a destination operand;
- a decoder circuitry to decode the fetched instruction;
- an execution circuitry to:
- execute the decoded by reversing the bit ordering for the source operand such that a least significant bit becomes a most significant bit;
- and
- store a resulting bit-reversed data into the destination operand.
3 more elements
Dependencies are inferred from the claim text.