Dual-clock fifo apparatus for packet transmission

Abstract

Disclosed is a dual-clock FIFO apparatus for packet transmission. The FIFO apparatus includes a multi-clock data queue which stores packets and has different read and write clock domains, a packet information queue configured to operate in the write clock domain and to store information data and a tail pointer for the packets, stored in the multi-clock data queue, when writing of packets to the multi-clock data queue is completed, a write state machine configured to operate in the write clock domain, and to read information and pointer data from the packet information queue and notify a read state machine that a packet is ready to read, and the read state machine configured to operate in a read clock domain, to determine whether a packet to be read is ready, and to monitor reading procedure of packet in the multi-clock data queue.

Dependencies are inferred from the claim text.