Memory buffer with one or more auxiliary interfaces
AssigneeInphi Corporation
InventorChristopher Haywood
Life of this patent
Estimating the term…
Abstract
The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.
Claims20
A computer system, comprising:
- a memory system, comprising:
- a plurality of DIMMs, each of which comprises a plurality of random access memory (RAM) chips;
- a plurality of memory buffers, each of which is coupled to at least one of said DIMMs, each of said memory buffers comprising:
- an interface arranged to buffer data and/or command bytes being written to or read from said plurality of DIMMs by a host controller;
- and
- at least one additional interface arranged to buffer data and/or command bytes between said first host controller and/or said DIMMs and one or more external devices coupled to said at least one additional interface.
A computer system, comprising:
- a common host CPU;
- a plurality of memory buffers coupled to said common host CPU via a plurality of memory channels;
- one or more DIMMs coupled to each of said memory buffers, each of said memory buffers comprising:
- an interface arranged to buffer data and/or command bytes being written to or read from said plurality of DIMMs by said common host CPU;
- and
- at least one additional interface arranged to buffer data and/or command bytes between said common host CPU and/or said DIMMs and one or more external devices coupled to said at least one additional interface.
Dependencies are inferred from the claim text.