Test IP-Based A.T.E. Instrument Architecture

A reconfigurable test system configured to seamlessly integrate automated testing of semiconductor devices between a pre-silicon simulation test phase, a post-silicon validation test phase, and a production test phase, in one embodiment of software and hardware across all three of the test phases, for different devices, said reconfigurable test system comprising:

• a tester instrument configured to be connected to a plurality of pins of a semiconductor device under test (DUT), said tester instrument comprising one or more FPGAs to thereby be reconfigurable, for use in the three phases of testing;
• multiple instances of Instrument IP (IIP) matched to each of one or more specific interfaces of a given DUT to provide functional and performance validation, characterization, and production test capabilities;
• a computer system configured with a user interface, said computer system comprising a controller, and configured to have said controller be connected to said reconfigurable tester instrument via a data bus;
• a test program stored on said controller, said test program and controller configured, when said program is executed, to instantiate said multiple instances of IIP into said reconfigurable tester instrument to be matched to device interfaces for each different DUT, and configured to execute a sequence of tests utilizing the IIP;
• an external memory;
• a protocol engine, said protocol engine configured to maintain an interface protocol to and from the DUT;
• a transaction processor, said transaction processor configured to take transactions from either said external memory or from a software executive, or to be algorithmically generated internally, and process and send them to said protocol engine;
• said transaction processor further configured to synchronize usage events by said multiple instances of Instrument IP, and configured to log events to save time-stamped transactions including pin-level detail into and out of the DUT, for each pin of the semiconductor DUT, and to store a log of the time-stamped transactions in said external memory;
• and
• a debug tool configured to graphically display the stored time-stamped pin-level transactions for each pin of the semiconductor DUT, both into and out of the DUT, and said debug tool further configured to compare said time-stamped transactions out of said pins to an expected response to help debug test cases and DUT errors, and said debug tool further configured to compare and display said transactions into and out of the DUT in a scoreboard format.