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US 2016/0233867 A1Published application
Frequency dividing circuit and semiconductor integrated circuit
AssigneeSocionext Inc.
InventorTetsuro TAMURA
Life of this patent
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Abstract
A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.
Claims13
A frequency dividing circuit comprising:
- a plurality of latch circuits that are connected in series in a loop in which the latch circuit driven at rising of a clock signal and the latch circuit driven at falling of the clock signal are alternately connected;
- and
- a generation circuit configured to generate a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of the plurality of latch circuits.
A semiconductor integrated circuit comprising:
- a plurality of latch circuits that are connected in series in a loop in which the latch circuit driven at rising of a clock signal and the latch circuit driven at falling of the clock signal are alternately connected;
- a generation circuit configured to generate a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of the plurality of latch circuits;
- and
- a conversion circuit configured to serial-parallel convert and output inputted serial data based on the plurality of frequency divided clock signals.
1 more element
A semiconductor integrated circuit comprising:
- a plurality of latch circuits that are connected in series in a loop in which the latch circuit driven at rising of a clock signal and the latch circuit driven at falling of the clock signal are alternately connected;
- a generation circuit configured to generate a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of the plurality of latch circuits;
- and
- a conversion circuit configured to parallel-serial convert and output inputted parallel data based on the plurality of frequency divided clock signals.
1 more element
Dependencies are inferred from the claim text.