# US 2016/0211348 A1 · Trench lateral diffusion metal oxide semiconductor device and manufacturing method of the same

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- Number: US 2016/0211348 A1
- Document ID: US20160211348A1
- Status: Published application
- Kind: A1
- Application number: 14/601,242
- Filed: 2015-01-21
- Published: 2016-07-21
- Earliest claimed: 2015-01-21
- Assignees: Maxchip Electronics Corp.
- Applicants: Maxchip Electronics Corp.
- Inventors: Kosuke Yoshida
- Web page: https://patentgrep.com/patent/US20160211348A1

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/0293: {using formation of insulating sidewall spacers}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 30/667: {having substrates comprising insulating layers, e.g. SOI-VDMOS transistors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 84/016: {the components including vertical IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A trench lateral diffusion metal oxide semiconductor (LDMOS) device, disposed on a substrate, comprising: a transistor and an LDMOS transistor. The transistor has a gate. The LDMOS transistor has a trench gate, wherein the trench gate protrudes from a surface of the substrate. Electrical connection of the trench gate and a doping region due to a metal silicide may be prevented by protruding the trench gate from the surface of the substrate. And furthermore a step height difference between a gate and the trench gate may be decreased, and openings respectively exposing a top portion of the trench gate and a top portion of the gate may be formed without changing the manufacturing conditions.

## Claims

### Claim 1

A trench LDMOS device, disposed on a substrate, comprising:
a transistor, disposed on a first area of the substrate, the transistor comprising a gate; and
a trench LDMOS transistor, disposed on a second area of the substrate, comprising:
a first well region, disposed in the second area of the substrate;
a second well region, having a first conductivity type, disposed in the first well region;
a trench gate, disposed in a trench of the substrate, wherein the trench gate protrudes from a surface of the substrate, and the trench is located in the second well region;
a gate dielectric layer, disposed between the trench gate and the substrate;
a first doped region, having the first conductivity type, disposed in the substrate at two sides of the trench gate; and
a second doped region, having a second conductivity type, disposed in the substrate between the trench gate and the first doped region.

### Claim 2 (depends on 1)

The trench LDMOS device as claimed in claim 1, wherein a step height of a portion of the trench gate protruding from the surface of the substrate is lower than a step height of the gate.

### Claim 3 (depends on 1)

The trench LDMOS device as claimed in claim 1, wherein a step height of a portion of the trench gate protruding from the surface of the substrate is higher than a step height of the gate.

### Claim 4 (depends on 1)

The trench LDMOS device as claimed in claim 1, further comprising a spacer, disposed on a side wall of a portion of the trench gate protruding from the surface of the substrate.

### Claim 5 (depends on 1)

The trench LDMOS device as claimed in claim 1, further comprising:
a third well region, having the second conductivity type, disposed in the first well region;
a third doped region, having the second conductivity type, disposed in the third well region; and
an element isolation structure, disposed in the substrate to isolate the second well region and the third well region.

### Claim 6 (depends on 1)

The trench LDMOS device as claimed in claim 1, wherein a depth of the trench is greater than a depth of a junction at a bottom of the second well region.

### Claim 7 (depends on 1)

The trench LDMOS device as claimed in claim 1, wherein the substrate is a silicon on insulator substrate.

### Claim 8 (depends on 7)

The trench LDMOS device as claimed in claim 7, wherein a bottom of the trench reaches an insulating layer of the silicon on insulator substrate.

### Claim 9 (depends on 8)

The trench LDMOS device as claimed in claim 8, further comprising:
a plurality of trench isolation structures, disposed in the substrate to isolate the first area and the second area, wherein each of the trench isolation structures respectively comprises a conductive layer and a dielectric layer disposed between the conductive layer and the substrate.

### Claim 10 (depends on 1)

The LDMOS device as claimed in claim 1, further comprising:
an embedded layer, having the first conductive type, disposed in the substrate, and located below the first well region; and
a plurality of trench isolation structures, disposed in the substrate to perforate the embedded layer and isolate the first area and the second area, wherein each of the trench isolation structures respectively comprises an insulation layer and a fourth doped region disposed at a bottom of the insulating layer.

### Claim 11 (depends on 5)

The trench LDMOS device as claimed in claim 5, further comprising a fifth doped region, having the second conductivity, connected two third doped regions respectively disposed in the third well regions on two sides of the second well region.

### Claim 12 (depends on 11)

The trench LDMOS device as claimed in claim 11, wherein the first well region alternately comprises the first conductivity and the second conductivity along an extension direction of the trench gate.

### Claim 13 (depends on 1)

The trench LDMOS device as claimed in claim 1, further comprising a sixth doped region, having the first conductivity, connected two first doped regions respectively disposed in two adjacent second well regions.

### Claim 14

A manufacturing method of a trench LDMOS device, comprising:
providing a substrate, the substrate comprising a first area and a second area;
forming a first well region at the second area of the substrate;
forming a second well region in the first well region;
forming a trench gate structure at the second area of the substrate, the trench gate structure protruding from a surface of the substrate, and located in the second well region, wherein the trench gate structure comprises a trench gate and a gate dielectric layer disposed between the trench gate and the substrate;
forming a first doped region on the surface of the substrate at two sides of the trench gate structure; and
forming a second doped region on the surface of the substrate between the trench gate structure and the first doped region.

### Claim 15 (depends on 14)

The manufacturing method of the trench LDMOS device as claimed in claim 14, further comprising forming a spacer on a side wall of a portion of the trench gate structure protruding from the surface of the substrate.

### Claim 16 (depends on 14)

The manufacturing method of the trench LDMOS device as claimed in claim 14, wherein the step of forming the trench gate structure at the second area of the substrate comprises:
forming a patterned mask layer on the substrate;
removing a portion of the substrate to form a trench in the substrate by using the patterned mask layer as a mask;
forming the gate dielectric layer on the surface of the trench;
removing the patterned mask layer;
forming a conductive layer filling the trench on the substrate; and
patterning the conductive layer to form the trench gate.

### Claim 17 (depends on 16)

The manufacturing method of the trench LDMOS device as claimed in claim 16, wherein the step of patterning the conductive layer further comprises:
forming a gate at the first area of the substrate.

### Claim 18 (depends on 14)

The manufacturing method of the trench LDMOS device as claimed in claim 14, wherein the step of forming the trench gate structure at the second area of the substrate comprises:
forming a first conductive layer on the substrate;
forming a patterned mask layer on the first conductive layer;
removing a portion of the first conductive layer and a portion of the substrate to form a trench in the substrate by using the patterned mask layer as a mask;
removing the patterned mask layer;
forming a dielectric layer on the surface of the first conductive layer and the trench;
forming a second conductive layer filling the trench on the substrate;
removing the second conductive layer to expose the dielectric layer;
removing a portion of the dielectric layer to form the gate dielectric layer; and
patterning the first conductive layer to form the trench gate.

### Claim 19 (depends on 18)

The manufacturing method of the trench LDMOS device as claimed in claim 18, wherein the step of patterning the first conductive layer further comprises:
forming a gate at the first area of the substrate.

### Claim 20 (depends on 18)

The manufacturing method of the trench LDMOS device as claimed in claim 18, wherein the step of removing the second conductive layer comprises performing a chemical mechanical polishing process.

### Claim 21 (depends on 14)

The manufacturing method of the trench LDMOS device as claimed in claim 14, wherein the step of forming the trench gate structure at the second area of the substrate comprises:
forming a first conductive layer on the substrate;
forming a sacrificial layer on the first conductive layer;
forming a patterned mask layer on the sacrificial layer;
removing a portion of the sacrificial layer, a portion of the first conductive layer and a portion of the substrate to form a trench in the substrate by using the patterned mask layer as a mask;
removing the patterned mask layer;
forming the gate dielectric layer on the surface of the trench;
forming a second conductive layer filling the trench on the substrate;
removing the second conductive layer to expose the sacrificial layer;
removing the sacrificial layer; and
patterning the first conductive layer to form the trench gate.

### Claim 22 (depends on 21)

The manufacturing method of the trench LDMOS device as claimed in claim 21, wherein the step of patterning the first conductive layer further comprises:
forming a gate at the first area of the substrate.

### Claim 23 (depends on 21)

The manufacturing method of the trench LDMOS device as claimed in claim 21, wherein the step of removing the second conductive layer comprises performing a chemical mechanical polishing process.

### Claim 24 (depends on 14)

The manufacturing method of the trench LDMOS device as claimed in claim 14, wherein the step of forming the trench gate structure at the second area of the substrate comprises:
forming a first conductive layer on the substrate;
forming a patterned mask layer on the first conductive layer;
removing a portion of the first conductive layer and a portion of the substrate to form a trench in the substrate by using the patterned mask layer as a mask;
forming the gate dielectric layer on the surface of the trench;
forming a second conductive layer filling the trench on the substrate;
removing the second conductive layer to expose the patterned mask layer;
removing the patterned mask layer; and
patterning the first conductive layer to form the trench gate.

### Claim 25 (depends on 24)

The manufacturing method of the trench LDMOS device as claimed in claim 24, wherein the step of patterning the first conductive layer further comprises:
forming a gate at the first area of the substrate.

### Claim 26 (depends on 24)

The manufacturing method of the trench LDMOS device as claimed in claim 24, wherein the step of removing the second conductive layer comprises performing a chemical mechanical polishing process.