US 2016/0164632 A1 · STAGGERED PARITY

Abstract

In a Forward Error Correction (FEC) technique, parity vectors are computed such that: each parity vector spans a set of frames; a subset of bits of each frame is associated with parity bits in each parity vector; and a location of parity bits associated with one frame in one parity vector is different from that of parity bits associated with the frame in another parity vector. Values of decoded hits of a first frame are deduced from known parity bits of a first parity vector having an effective length of one frame. For parity vectors having, an effective length greater than one frame, a Log Likelihood Ratio of each unknown parity bit associated with the first frame is updated based on known and unknown parity bits of each parity valor. The first frame is decoded using the deduced bit values and the updated LLR values.

Claims21

Dependent claims

A method of forward error correction, the method comprising a FEC encoder:

processing a data signal to generate a sequence of FEC frames;
and
computing a plurality of parity vectors such that
each parity vector spans a plurality of the FEC frames,
a subset of N (where N is an integer, N>0) bits of a FEC frame is allocated to each one of at least two parity vectors, and
a respective location of the subset of N bits from a given FEC frame within one parity vector is different than the respective location of the subset of N bits from the FEC frame within another parity vector, such that the plurality of parity vectors are staggered with respect to a sequence in which the FEC frames are processed.

3 more elements

Dependencies are inferred from the claim text.

Staggered parity

Life of this patent

Staggered parity

Life of this patent

Abstract

Claims21