Three-dimensional memory structure having a back gate electrode

A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:

• applying a positive voltage to the back gate electrode;
• and
• applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string,
• wherein an absolute value of the positive voltage applied to the back gate electrode is smaller than an absolute value of the negative read voltage applied to the selected control gate electrode.

A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:

• applying a positive voltage to the back gate electrode;
• applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
• applying a voltage between a source and a drain of the NAND string;
• and
• determining that charge is stored in a charge storage region of the memory film of the selected cell if no current flows between the source and the drain during application of the positive voltage to the back gate electrode and the negative read voltage of the selected control gate electrode.

A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:

• applying a positive voltage to the back gate electrode;
• applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
• applying a voltage between a source and a drain of the NAND string;
• and
• determining that no charge is stored in a charge storage region of the memory film of the selected cell if current flows between the source and the drain during application of the positive voltage to the back gate electrode and the negative read voltage of the selected control gate electrode.

A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:

• applying a positive voltage to the back gate electrode;
• applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
• applying a voltage between a source and a drain of the NAND string;
• applying a first pair of electrical bias conditions comprising applying a first backside bias voltage to the back gate electrode and a first control gate bias voltage to the control gate electrode of the selected cell;
• applying a second pair of electrical bias conditions comprising applying a second backside bias voltage to the back gate electrode and a second control gate bias voltage to the control gate electrode of the selected cell, wherein:
• (i) the first and the second backside bias voltages are the same and the first and the second control gate bias voltages are different, or
• (ii) the first and the second backside bias voltages are different and the first and the second control gate bias voltages are the same;
• and
• determining a total amount of electrical charge stored in a charge storage region of the memory film of the selected cell when an electrical current through the semiconductor channel is above a predefined threshold level for the first pair of electrical bias conditions, and is below a predefined threshold level for the second pair of electrical bias conditions.