Signal processing device

A signal processing device comprising:

• a first clock generation circuit to generate a first clock rising at a time which is delayed by αT (0<α<0.5) from a transition point of each data of a received signal having a time period of T which is Manchester-encoded;
• a second clock generation circuit disposed in parallel with said first clock generation circuit, to generate a second clock rising at a time which is delayed by βT (0<β<0.5), βT being different from said αT, from the transition point of each data of said received signal;
• a data detection circuit to output first and second detection results of said received signal on a basis of said first and second clocks;
• and
• a determination circuit to perform determination on the received signal on a basis of said first and second detection results.

A signal processing device comprising:

• a first clock generation circuit to generate a first clock rising at a time which is delayed by αT (0.5<α<1.0) from a transition point of each data of a received signal having a time period of T which is Manchester-encoded;
• a second clock generation circuit disposed in parallel with said first clock generation circuit, to generate a second clock rising at a time which is delayed by βT (0<β<0.5) from the transition point of each data of said received signal;
• a data detection circuit to output first and second detection results of said received signal on a basis of said first and second clocks;
• and
• a determination circuit to perform determination on the received signal on a basis of said first and second detection results.