US 2016/0112200 A1 · CRYPTOGRAPHIC HASHING CIRCUITRY HAVING IMPROVED SCHEDULING EFFICIENCY

Abstract

Cryptographic hashing circuitry such as mining circuitry used to mine digital currency may be formed on an integrated circuit. The hashing circuitry may include sequential rounds of register and logic circuitry that perform operations of a cryptographic protocol. A final hash value output by the hashing circuitry may include hash values stored at previous rounds of the cryptographic hashing circuitry. The hashing circuitry may be formed with only two registers per round, thereby optimizing chip area consumption. The hashing circuitry may perform sequential rounds of cryptographic hashing based on an initial hash value and multiple message words. One or more message registers may store the message words. Control circuitry may selectively route the message words from the message register to the hashing circuitry using pointers. If desired, the message registers may be replaced by one or more arrays of memory elements read using row and column pointers.

Claims30

Dependent claims

Cryptographic hashing circuitry on an integrated circuit, comprising:

a first register that stores a first hash value;
logic circuitry that is configured to generate a second hash value based on at least the stored first hash value;
and
a second register that stores the second hash value, wherein the second register is configured to output the stored second hash value as part of a hash output value, the first register is configured to directly output the stored first hash value as part of the hash output value, and the first hash value is different from the second hash value.

1 more element

An electronic device that forms a node in a peer-to-peer network of nodes that support transactions in a digital currency, the electronic device comprising:

hashing circuitry configured to perform a plurality of sequential rounds of a Secure Hash Algorithm 256 (SHA-256) cryptographic hashing algorithm based at least on an initial hash value and a plurality of message words;
a memory array that is configured to store the plurality of message words;
and
control circuitry, wherein the control circuitry is configured to selectively route the plurality of message words from the memory array to the hashing circuitry.

1 more element

Dependencies are inferred from the claim text.

Cryptographic hashing circuitry having improved scheduling efficiency

Life of this patent

Cryptographic hashing circuitry having improved scheduling efficiency

Life of this patent

Abstract

Claims30