Cryptographic device for implementing s-box

An integrated circuit (IC) having a cryptographic function, the IC, comprising:

• a decoder comprising a plurality of circuit logic gates configured to receive an input signal consisting of k bits;
• and
• an encoder configured to receive an output signal from the plurality of circuit logic gates of the decoder and to encode the received output signal to generate an output signal having m bits,
• wherein the decoder is configured to generate n number of logic ‘1’ in response to any input signal,
• wherein each of k, m and n is a positive integer, and
• wherein k is greater than m.

An integrated circuit (IC) having a cryptographic function, the IC comprising:

• a plurality of first circuit logic gates configured to receive an input signal having a plurality of bits;
• a plurality of second circuit logic gates, each of the plurality of second circuit logic gates being configured to receive outputs of corresponding first circuit logic gates;
• a plurality of third circuit logic gates, each of the plurality of third circuit logic gates being configured to receive outputs of corresponding second circuit logic gates;
• and
• an encoder configured to receive outputs of the plurality of third circuit logic gates and to output an encoded signal having a plurality of bits,
• wherein each of a plurality of values of the encoded signal corresponds to at least two values of a plurality of values of the input signal, each value of the encoded signal being represented by the plurality of bits of the encoded signal, each value of the input signal being represented by the plurality of bits of the input signal,
• wherein, for any value of the plurality of bits of the input signal, a predetermined number of the first circuit logic gates from among the plurality of first circuit logic gates output logic “1” and the remaining first circuit logic gates output logic “0”,
• wherein, for any value of the plurality of bits of the input signal, a predetermined number of the second circuit logic gates from among the plurality of second circuit logic gates output logic “1” and the remaining second circuit logic gates output logic “0”, and
• wherein, for any value of the plurality of bits of the input signal, a predetermined number of the third circuit logic gates from among the plurality of third circuit logic gates output logic “1” and the remaining third circuit logic gates output logic “0”.