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US 2016/0112068 A1Published application
Controller, semiconductor memory system, data storage system and operating method thereof
AssigneeSK hynix Inc.
InventorJae-Bum KIM
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Abstract
An operating method of a controller includes iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding.
Claims18
An operating method of a controller, comprising:
- iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC);
- and
- when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding.
An operating method of a controller, comprising:
- a first step of performing a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage;
- a second step of determining the first ECC decoding to have failed or succeeded based on an unsatisfied syndrome check (USC) included in a result of the first ECC decoding;
- a third step of updating a value of the first read voltage based on a number of the USC when the first ECC decoding is determined to have failed;
- and
- a fourth step of iterating the first to third steps a predetermined iteration number until the first ECC decoding succeeds.
2 more elements
A controller comprising:
- means for iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC);
- and
- means for performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iteration of the first ECC decoding, when the first ECC decoding fails until the predetermined iteration number.
A controller comprising:
- first means for performing a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage;
- second means for determining the first ECC decoding to have failed or succeeded on the basis of an unsatisfied syndrome check (USC) included in a result of the first ECC decoding;
- and
- third means for updating a value of the first read voltage based on a number of the USC when the first ECC decoding is determined to have failed,
- wherein the controller iterates the operations of the first to third means a predetermined iteration number until the first ECC decoding succeeds.
2 more elements
A semiconductor memory system comprising:
- a semiconductor memory device;
- and
- a controller,
- wherein the controller comprises:
- means for iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC);
- and
- means for performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding, when the first ECC decoding fails until the predetermined iteration number.
4 more elements
A semiconductor memory system comprising:
- a semiconductor memory device;
- and
- a controller,
- wherein the controller comprises:
- first means for performing a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage;
- second means for determining the first ECC decoding to have failed or succeeded on the basis of an unsatisfied syndrome check (USC) included in a result of the first ECC decoding;
- and
- third means for updating a value of the first read voltage based on a number of the USC when the first ECC decoding is determined to have failed, and
- wherein the controller iterates the operations of the first to third means a predetermined iteration number until the first ECC decoding succeeds.
6 more elements
Dependencies are inferred from the claim text.