Phase frequency detector (pfd) circuit with improved lock time
AssigneeTexas Instruments Incorporated
InventorsPeeyoosh Nitin Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan
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Abstract
Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
Claims26
A locking circuit to provide a clock output signal according to a reference clock signal, comprising:
- a controlled oscillator including an output to provide an oscillator output clock signal according to a control voltage signal;
- a feedback circuit including a first output to provide a feedback clock signal according to the oscillator output clock signal;
- a loop filter circuit comprising an impedance and a second output to provide the control voltage signal according to a current signal;
- a charge pump circuit including a third output to generate the current signal according to a control input signal;
- and
- a phase frequency detector (PFD) circuit operative in a first mode to generate the control input signal having a pulse width corresponding to a phase difference between a reference clock signal and the feedback clock signal, and operative in a second mode to generate the control input signal with a constant value;
- and
- a mode control circuit operative to place the PFD circuit in the first mode when the phase difference between the reference clock signal and the feedback clock signal is less than a predetermined value, and operative in response to the phase difference exceeding the predetermined value to place the PFD circuit in the second mode for a predetermined time.
A circuit to control lock time of a locking circuit, the control circuit comprising:
- a phase frequency detector (PFD) circuit to generate first and second control input signals to operate a charge pump circuit to cause the charge pump circuit to drive a controlled oscillator that generates an oscillating output signal of the locking circuit, the PFD circuit including a first PFD flip-flop including a first PFD flip-flop clock input to receive a reference clock signal, and a first PFD flip-flop output to generate the first control input signal, and a second PFD flip-flop including a second PH) flip-flop clock input to receive a feedback clock signal derived from the oscillating output signal, and a second PFD flip-flop output to generate the second control input signal;
- and
- a control circuit to detect cycle slip conditions in the locking circuit when a phase difference between the reference clock signal and the feedback clock signal exceeds a predetermined value, the control circuit operative to generate a mode control signal in response to a detected cycle slip condition to cause the PFD circuit to hold the first and second control input signals at constant values for a predetermined time.
A method to control lock time of a phase lock loop, the method comprising:
- generating a control input signal to operate a controlled oscillator circuit of a phase lock loop, the control input signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal when the phase difference is less than a predetermined value;
- and
- selectively holding the control input signal at a constant value for a predetermined time in response to the phase difference exceeding the predetermined value.
Dependencies are inferred from the claim text.