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US 2016/0112053 A1Published application
Fractional-N Phase-Locked Loop
AssigneeSilicon Laboratories Inc.
InventorMichael H. Perrott
Life of this patent
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Abstract
A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.
Claims19
A phase-locked loop (PLL) comprising:
- a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage signal with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal based on an output of a first oscillator, the first oscillator controlled at least in part based on a value of the combined voltage signal;
- and
- an oscillator-based analog to digital converter (ADC) coupled the capacitor based DAC to convert the combined voltage signal to a digital value, the oscillator-based ADC having a second oscillator having a frequency responsive to the combined voltage signal.
A method of operating a fractional-N phase-locked loop (PLL) comprising:
- converting a phase error corresponding to a time difference between a reference signal and a feedback signal of the PLL to one or more voltage signals;
- reducing quantization noise in the one or more voltage signals using one or more capacitor-based digital to analog converters (DACs) and generating one or more combined voltage signals with reduced quantization noise, the one or more combined voltage signals corresponding to a phase difference with reduced quantization noise;
- controlling a frequency of an oscillator in an oscillator-based analog to digital converter (ADC) according to the one or more combined voltages;
- and
- determining a digital value in the oscillator-based ADC corresponding to the phase difference with reduced quantization noise based on the frequency.
2 more elements
Dependencies are inferred from the claim text.