Flip-flop cell with configurable delay
AssigneeFreescale Semiconductor, Inc.
InventorsGaurav Goyal, Ashis Maitra, Ateet Mishra
Life of this patent
Estimating the term…
Abstract
Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.
Claims18
An integrated circuit (IC), comprising:
- logic cells and flip-flop cells, wherein the flip-flop cells are connected with the logic cells in functional data paths in a functional mode of operation, and are connected together in scan data paths in a scan test mode of operation for shifting scan test data through the IC;
- and
- a selective delay cell connected to a selected one of the flip-flop cells, the selected flip-flop cell having a clock signal controlling both the input and output thereof, wherein the selective delay cell modifies a delay of one of a data signal input to the selected flip-flop cell and the clock signal controlling the flip-flop cell,
- wherein the selected delayed signal adjusts the timing of the functional data path.
A method of adjusting timing in an integrated circuit (IC) design, the design including logic cells and flip-flop cells, using an electronic design automation (EDA) tool, wherein the flip-flop cells are connected with the logic cells to form functional data paths in a functional mode of operation, and are connected together to form scan data paths in a scan test mode of operation for shifting scan test data through the IC, the method comprising:
- identifying critical timing in a data path including a first flip-flop cell that has a clock signal controlling both its input and output, using the EDA tool;
- and
- connecting a selective delay cell to the first flip-flop cell, using the EDA tool, wherein the selective delay cell selectively delays one of a data signal input to the first flip-flop cell and the clock signal controlling the first flip-flop cell,
- wherein the selectively delayed signal adjusts the timing of the functional data path.
A non-transitory computer-readable storage medium storing instructions for execution by an electronic design automation (EDA) tool including a processor and a memory coupled to the processor which, when executed by the EDA tool, cause the EDA tool to perform a method of adjusting timing in an integrated circuit (IC) design stored in the memory, wherein the IC design includes logic cells and flip-flop cells, wherein the flip-flop cells are connected with the logic cells to form functional data paths in a functional mode of operation, and are connected together for form scan data paths in a scan test mode of operation for shifting scan test data through the IC, the method comprising:
- identifying critical timing in a data path including a flip-flop cell that has a clock signal controlling both its input and output;
- and
- connecting a selective delay cell to the flip-flop cell, the selective delay cell selectively delaying one of a data signal input to the flip-flop cell and the clock signal controlling the flip-flop cell,
- wherein the selectively delayed signal adjusts the timing of the functional data path.
Dependencies are inferred from the claim text.