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US 2016/0112033 A1Published application
Efficient implementation of cascaded biquads
AssigneeTexas Instruments Incorporated
InventorsAsheesh Bhardwaj, Lester A. Longley
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Abstract
An improved biquad infinite impulse response filter is shown that may be implemented in a very large instruction word digital signal processor as well as in other processing circuitry. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles.
Claims5
A method of performing infinite impulse response filtering, the method comprising the steps of:
- computing the filter output by setting
- out=in+d0
- t1=(b1+a1)*in+d0
- t0=a2*d0
- d0=a1*d0
- d1=(b2+a2)*in+t0
- where a1, a2, b1, b2 are coefficients and d0, d1, t0, t1 are intermediate results.
4 more elements
An apparatus for performing infinite impulse response filtering, the apparatus comprising:
- a digital signal processor operable to compute the filter output by performing the following steps:
- out=in+d0
- t1=(b1+a1)*in+d0
- t0=a2*d0
- d0=a1*d0
- d1=(b2+a2)*in+t0
- where a1, a2, b1, b2 are coefficients and d0, d1, t0, t1 are intermediate results.
4 more elements
Dependencies are inferred from the claim text.