Low noise amplifier and chip

A low noise amplifier, comprising:

• a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input, a first signal output, a second amplifying circuit unit, a second adjusting unit and a second signal output, wherein,
• the biasing circuit unit is configured to provide a biasing voltage for the first amplifying circuit unit and the second amplifying circuit unit, and comprises a first voltage output and a second voltage output;
• the first amplifying circuit unit comprises a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance, and a second impedance;
• the second amplifying circuit unit comprises a second N-type transistor, a second P-type transistor, a third output capacitor, a fourth output capacitor, a third impedance, and a fourth impedance;
• a gate of the first N-type transistor is connected to the first voltage output of the biasing circuit unit by means of the first adjusting unit, and is connected to the second signal input by means of the first adjusting unit;
• a gate of the first P-type transistor is connected to the second voltage output of the biasing circuit unit by means of the first adjusting unit, and is connected to the second signal input by means of the first adjusting unit;
• a source of the first N-type transistor is connected to a source of the first P-type transistor, and both sources are connected to the second signal input;
• a drain of the first N-type transistor is connected to the first impedance, and is connected to the first signal output by means of the first output capacitor, and a drain of the first P-type transistor is connected to the second impedance, and is connected to the first signal output by means of the second output capacitor;
• a gate of the second N-type transistor is connected to the first voltage output of the biasing circuit unit by means of the second adjusting unit, and is connected to the first signal input by means of the second adjusting unit;
• a gate of the second P-type transistor is connected to the second voltage output of the biasing circuit unit by means of the second adjusting unit, and is connected to the first signal input by means of the second adjusting unit;
• a source of the second N-type transistor is connected to a source of the second P-type transistor, and both sources are connected to the first signal input;
• a drain of the second N-type transistor is connected to the third impedance, and is connected to the second signal output by means of the third output capacitor, and a drain of the second P-type transistor is connected to the fourth impedance, and is connected to the second signal output by means of the fourth output capacitor;
• the gate of the first N-type transistor is connected to the gate of the second N-type transistor by means of the first adjusting unit and the second adjusting unit, the gate of the first P-type transistor is connected to the gate of the second P-type transistor by means of the first adjusting unit and the second adjusting unit;
• the biasing circuit unit is connected between a high voltage end and a low voltage end of a voltage source, the first impedance of the first amplifying circuit unit is connected to the high voltage end of the voltage source, and the second impedance of the first amplifying circuit unit is connected to the low voltage end of the voltage source;
• the third impedance of the second amplifying circuit unit is connected to the high voltage end of the voltage source, and the fourth impedance of the second amplifying circuit unit is connected to the low voltage end of the voltage source;
• wherein the biasing circuit unit comprises a first current source, a third N-type transistor, a third P-type transistor and a second current source which are serially connected between the high voltage end and the low voltage end of the voltage source, and further comprises a first voltage output and a second voltage output;
• wherein, a gate of the third N-type transistor is connected to a drain of the third N-type transistor, a gate of the third P-type transistor is connected to a drain of the third P-type transistor;
• a source of the third N-type transistor is connected to a source of the third P-type transistor, the gate of the third N-type transistor and the gate of the third P-type transistor are connected to the first voltage output and the second voltage output respectively.