Digital controlled oscillator and switchable varactor for high frequency low noise operation

A switchable varactor circuit for providing a switchable capacitance between first and second varactor nodes, the switchable varactor circuit comprising:

• a first capacitance coupled between the first varactor node and a first internal node;
• a second capacitance coupled between the second varactor node and a second internal node;
• a first transistor with a first control terminal for receiving a control signal, the first transistor selectively operable to couple the first internal node with the second internal node to provide a first capacitance between the first and second varactor nodes when the control signal is in a first state, and to decouple the first internal node from the second internal node to provide a second lower capacitance between the first and second varactor nodes when the control signal is in a different second state;
• a second transistor with a second control terminal for receiving the control signal, the second transistor selectively operable to couple the first internal node with a third internal node when the control signal is in the first state, and to decouple the first internal node from a third internal node when the control signal is the second state;
• a third transistor with a third control terminal for receiving the control signal, the third transistor selectively operable to couple the second internal node with the third internal node when the control signal is in the first state, and to decouple the second internal node from the third internal node when the control signal is the second state;
• and
• a fourth transistor with a fourth control terminal for receiving the control signal, the fourth transistor selectively operable to couple the third internal node with a supply voltage node when the control signal is the second state.

A switchable capacitance circuit, comprising:

• a control input for receiving a switching control input signal;
• a first capacitance including a first terminal coupled with a first output node, and a second terminal coupled with a first internal node;
• a second capacitance including a first terminal coupled with a second output node, and a second terminal coupled with a second internal node;
• a first transistor including a source coupled with the first internal node, a drain coupled with the second internal node, and a gate coupled with the control input to turn the first transistor on when the switching control input signal is in the first state and to turn the first transistor off when the switching control signal is in the second state;
• a second transistor including a drain coupled with the first internal node, a source coupled with a third internal node, and a gate coupled with the control input to turn the second transistor on when the switching control input signal is in the first state and to turn the second transistor off when the switching control signal is in the second state;
• a third transistor including a drain coupled with the second internal node, a source coupled with the third internal node, and a gate coupled with the control input to turn the third transistor on when the switching control input signal is in the first state and to turn the third transistor off when the switching control signal is in the second state;
• and
• an inverter circuit with an inverter input node coupled with the control input, and an inverter output node controlling a voltage at the third internal node according to the switching control input signal.