Dividing a single phase pulse-width modulation signal into a plurality of phases
AssigneeLenovo (Singapore) Pte.Ltd.
InventorsJAMAICA L. BARNETTE, LUKE D. REMIS
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Abstract
Dividing a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level.
Claims14
A method of dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the method comprising:
- receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period;
- and
- dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train:
- providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train;
- and
- holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.
An apparatus for dividing a single phase pulse-width modulation (PWM) signal into a plurality of phases, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
- receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period;
- and
- dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train:
- providing, on a next output phase of the PWM frequency divider, an output pulse train that transitions from a tri-state voltage level to a logic high voltage level at the onset of a period of the input pulse train and transitions from the logic high voltage level to a logic low voltage level toward the end of the period of the input pulse train;
- and
- holding all other output phases at the tri-state voltage level that is between the logic high voltage level and the logic low voltage level.
Dependencies are inferred from the claim text.