Chip package and method of manufacturing the same

A method of manufacturing chip package, comprising:

• providing a semiconductor wafer having a plurality of semiconductor chips, the semiconductor chips arranged in an array, each of the semiconductor chips having at least an electronic component and at least an electrically conductive pad disposed on an upper surface of the semiconductor chip, the conductive pad arranged abreast to one side of the electronic component and electrically connected to the electronic component;
• forming an outer spacer and a plurality of inner spacers on the semiconductor wafer, wherein the outer spacer separates each of the semiconductor chips, and each of the inner spacers surrounds the electronic component on each of the semiconductor chips;
• forming a protection lid disposed on the outer spacer and the inner spacers;
• forming a plurality of cavities from a lower surface of each of the semiconductor chips to expose the conductive pad disposed on the upper surface;
• forming a plurality of conductive portions filling each of the cavities from the lower surface and electrically connected to each of the conductive pads;
• forming a plurality of conductive structures disposed on the lower surface and electrically connected to each of the conductive portions;
• and
• cutting along a plurality of cutting lines between each of the semiconductor chips to separate each of the semiconductor chips,
• wherein the outer spacer and the inner spacers are separate, and the cutting lines go through the outer spacer alone, rather than the inner spacers.