Methods of forming a semiconductor circuit element and semiconductor circuit element
AssigneeGlobalfoundries Inc.
InventorsPeter Baars, Carsten Grass
Life of this patent
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Abstract
The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.
Claims20
A method of forming a semiconductor circuit element having a first semiconductor device and a second semiconductor device, the method comprising:
- forming said first semiconductor device in and above a first active region of a semiconductor substrate, said first semiconductor device comprising a first gate structure with a first gate dielectric layer;
- and
- forming said second semiconductor device in and above a second active region of said semiconductor substrate, said second semiconductor device comprising a second gate structure with a second gate dielectric layer;
- wherein said first gate dielectric layer is formed by forming a buried ferroelectric material in said first active region, and
- wherein said second gate dielectric layer is formed by forming a high-k material above said second active region, said high-k material being different from said ferroelectric material.
A method of forming a semiconductor circuit element, the method comprising:
- forming a recess in a first active region of a semiconductor substrate;
- forming a ferroelectric material in said recess;
- forming a high-k material over a second active region of said semiconductor substrate adjacent to said first active region, said high-k material being different from said ferroelectric material;
- forming a gate electrode material over said first and second active regions;
- forming a first gate structure over said first active region by patterning said ferroelectric high-k material and said gate electrode material;
- and
- forming a second gate structure over said second active region by patterning said high-k material and said gate electrode material.
A method of forming a semiconductor circuit element, the method comprising:
- forming a recess in a first active region of a semiconductor substrate;
- forming an amorphous film of material in said recess, said amorphous film of material exhibiting ferroelectric behavior in a crystalline phase;
- forming a first cap layer that covers said amorphous film of material;
- forming a high-k material over a second active region of said semiconductor substrate after said cap layer is formed over said amorphous film of material, said high-k material being different from said amorphous film of material;
- crystallizing said amorphous film of material for forming a ferroelectric material buried in said first active region;
- forming a first gate dielectric layer over said first active region by patterning said ferroelectric material;
- and
- forming a second gate dielectric layer over said second active region by patterning said high-k material.
A semiconductor circuit element, comprising:
- a first semiconductor device formed over and in a first active region of a semiconductor substrate, said first semiconductor device comprising first source/drain regions and a first gate structure with a first gate dielectric layer;
- and
- a second semiconductor device formed over and in a second active region of said semiconductor substrate, said second semiconductor device comprising second source/drain regions and a second gate structure with a second gate dielectric layer;
- wherein said first gate dielectric layer comprises a ferroelectric material and said second gate dielectric layer comprises a high-k material different from said ferroelectric material;
- and
- wherein an upper surface of said first active region below said first gate structure is positioned at a height level that is lower in said semiconductor substrate relative to an upper surface of said second active region.
Dependencies are inferred from the claim text.