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US 2016/0111539 A1Published application
HIGH MOBILITY PMOS AND NMOS DEVICES HAVING Si-Ge QUANTUM WELLS
AssigneeGlobalfoundries Inc.
InventorDeepak Kumar Nayak
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Abstract
At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer.
Claims20
A method for providing a semiconductor base structure, comprising:
- forming a substrate;
- forming a strained relaxed layer on said substrate;
- forming a first tensile strained layer on said strained relaxed layer;
- and
- forming a first compressive strain layer on said first tensile strained layer.
2 more elements
A semiconductor device, comprising:
- a silicon substrate;
- a strained relaxed layer positioned on said silicon substrate;
- and
- a quantum well layer positioned on said strained relaxed layer, wherein said quantum well layer comprising a tensile strained layer positioned on said strained relaxed layer, and a compressive strain layer on said tensile strained layer;
- and
- wherein said semiconductor base substrate is capable of providing an enhanced current drive for at least one of a NMOS device and a PMOS device formed on said quantum well layer.
3 more elements
A system, comprising:
- a semiconductor device processing system to provide an integrated circuit device, wherein said integrated circuit device comprises:
- a silicon substrate;
- a strained relaxed layer positioned on said silicon substrate;
- and
- a quantum well layer positioned on said strained relaxed layer wherein said quantum well layer comprising a tensile strained layer positioned on said strained relaxed layer, and a compressive strain layer on said tensile strained layer;
- and
- wherein said semiconductor base substrate is capable of providing an increased current drive for at least one of a NMOS device and a PMOS device formed on said quantum well layer;
- and
- a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system.
6 more elements
Dependencies are inferred from the claim text.