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US 2016/0111533 A1Published application
Silicon carbide semiconductor device
AssigneeHestia Power Inc.
InventorsCheng-Tyng YEN, Chien-Chung HUNG, Chwan-Ying LEE, Lurng-Shehng LEE
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Abstract
A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
Claims25
A silicon carbide (SiC) semiconductor device, comprising:
- an n-type substrate, having a first doping concentration;
- an n-type drift layer, disposed on the substrate, having a second doping concentration less than the first doping concentration;
- a plurality of doped regions, disposed at the n-type drift layer, spaced from each other and formed a junction field effect transistor (JFET) region having a third doping concentration therebetween, each of the doped regions comprising a p-well, a heavily doped n-type (n+) region located in the p-well, and a heavily doped p-type (p+) region;
- a gate dielectric layer, disposed on the n-type drift layer;
- a gate electrode, disposed on the gate dielectric layer;
- an inter-layer dielectric layer, disposed on the gate dielectric layer 41 and the gate electrode;
- a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the n+ region and the p+ region and are separated by the gate electrode and the inter-layer dielectric layer;
- a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the JFET region and the doped regions are separated by the gate electrode and the inter-layer dielectric layer;
- a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;
- a first metal layer, disposed at a bottom of the source openings, formed an Ohmic contact with the surface portion of the n+ region and the p+ region;
- and
- a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings is electrically connected to the first metal layer and forms a Schottky contact with the surface portion of the JFET region, the second portion covers the gate openings and is electrically insulated from the first portion.
9 more elements
The SiC semiconductor device of claim I, wherein the first metal layer comprising a silicide or a combination of suicides of a material selected from a group consisting of nickel, titanium, aluminum, molybdenum and niobium.
A. silicon carbide (SiC) semiconductor device, comprising:
- an n-type substrate, having a first doping concentration;
- an n-type drift layer, disposed on the substrate, having a second doping concentration less than the first doping concentration;
- a plurality of first doped regions and a plurality of second doped regions, disposed at the n-type drift layer, each of the first doped regions comprising a first p-well, a heavily doped n-type (n+) region located in the first p-well, and a first heavily doped p-type (p+) region located in the first p-well and surrounded by the n+ region, each of the second doped regions comprising at least one sub-doped region, wherein a first junction field effect transistor (JFET) region having a third doping concentration formed between each of the first doped regions and the second doped regions and a second junction field effect transistor (JFET) region having a fourth doping concentration formed between each of the sub-doped regions or enclosed by the sub-doped region;
- a gate dielectric layer, disposed on the n-type drift layer;
- a gate electrode, disposed on the gate dielectric layer;
- an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode;
- a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the n+ region and the first p+ region and are separated by the gate electrode and the inter-layer dielectric layer;
- a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the second JFET region and the second doped regions are separated by the gate electrode and the inter-layer dielectric layer;
- a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;
- a first metal layer, disposed at a bottom of the source openings, formed an Ohmic contact with the surface portion of the n+ region and the first p+ region;
- and
- a second metal layer, comprising a first portion and a second portion, wherein the first portion covers the source openings and the junction openings is electrically connected to the first metal layer and forms a Schottky contact with the surface portion of the second JFET region, the second portion covers the gate openings and is electrically insulated from the first portion.
9 more elements
Dependencies are inferred from the claim text.