Dual gate structure

A method for forming a dual gate structure for a vertical TFT, comprising:

• forming one or more polysilicon layers;
• forming a plurality of oxide pillars, the forming a plurality of oxide pillars includes etching a plurality of trenches extending through the one or more polysilicon layers and filling the plurality of trenches with an insulating material, the plurality of oxide pillars includes a first set of oxide pillars and a second set of oxide pillars different from the first set of oxide pillars;
• forming a first set of trenches by etching the first set of oxide pillars to a first depth;
• forming a second set of trenches by etching the second set of oxide pillars to a second depth higher than the first depth;
• forming a plurality of gate dielectrics within the first set of trenches and the second set of trenches;
• forming a first set of gate structures and a second set of gate structures, the forming the first set of gate structures and the second set of gate structures includes filling the first set of trenches and the second set of trenches with a gate material subsequent to the forming the plurality of gate dielectrics;
• forming a third set of trenches by etching the first set of gate structures to a third depth;
• forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth;
• and
• filling the third set of trenches and the fourth set of trenches with the insulating material.

A method for manufacturing a semiconductor memory, comprising:

• forming one or more vertical TFTs, the forming one or more vertical TFTs includes performing a first etching process, the first etching process includes etching a first set of oxide pillars of a plurality of oxide pillars to a first initial depth, the plurality of oxide pillars includes a second set of oxide pillars different from the first set of oxide pillars, the forming one or more vertical TFTs includes performing a second etching process subsequent to the performing the first etching process, the second etching process forms a first set of trenches by etching the first set of oxide pillars from the first initial depth to a first depth, the second etching process forms a second set of trenches by etching the second set of oxide pillars to a second depth higher than the first depth, the first depth and the second depth are both lower than the first initial depth, the forming one or more vertical TFTs includes forming a plurality of gate dielectrics within the first set of trenches and the second set of trenches, the forming one or more vertical TFTs includes forming a first set of gate structures and a second set of gate structures, the forming the first set of gate structures and the second set of gate structures includes filling the first set of trenches and the second set of trenches with a gate material subsequent to the forming the plurality of gate dielectrics;
• and
• forming a memory array above the one or more vertical TFTs, the memory array includes a first bit line, the one or more vertical TFTs include a first vertical TFT connected to the first bit line.