Air gap spacer integration for improved fin device performance

A method for providing a FinFET device with an air gap spacer, comprising:

• providing a substrate including a plurality of fins and a dummy gate arranged transverse to the plurality of fins;
• depositing a sacrificial spacer around the dummy gate;
• depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer;
• selectively etching the dummy gate relative to the first ILD layer and the sacrificial spacer;
• depositing a replacement metal gate (RMG);
• etching a portion of the RMG to create a recess surrounded by the sacrificial spacer;
• and
• depositing a gate capping layer in the recess, wherein the gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).

A FinFET device comprising:

• a plurality of fins ;
• a source contact arranged in contact with first ends of the plurality of fins;
• a drain contact arranged in contact with second ends of the plurality of fins;
• and
• a metal gate arranged between and spaced from the source contact and the drain contact and in contact with the plurality of fins, wherein the metal gate includes a gate capping layer made of silicon oxycarbide (SiOC).

A FinFET device comprising:

• a plurality of fins;
• a source contact in contact with first ends of the plurality of fins;
• a drain contact in contact with second ends of the plurality of fins;
• a metal gate arranged between and spaced from the source contact and the drain contact and in contact with the plurality of fins;
• a first interlayer dielectric (ILD) layer;
• and
• an air gap located between the first ILD layer and the metal gate, between the source contact and the gate and between the drain contact and the gate.