Ultra-low resistance gate structure for non-planar device via minimized work function material

Abstract

A non-planar semiconductor structure includes an ultra-low resistance gate structure. The non-planar structure includes a semiconductor substrate and raised semiconductor structures coupled to the substrate, a lower portion of the raised structures surrounded by a layer of isolation material. The structure further includes gate structures surrounding an upper portion of the raised structures, the gate structures including a conductive material and a layer of work function material present only in a limited area surrounding each raised structure. The limited area of work function material is achieved in fabrication by including dummy gate structures covering a layer of selectively removable material above the raised structures and a layer of hard mask material above the selectively removable layer, removing the selectively removable layer with the dummy gate structures, filling the resulting gate openings with work function material and then removing most of it, using the layer of hard mask material to delimit the limited area of work function material.

Dependencies are inferred from the claim text.