Transistor with performance boost by epitaxial layer

A transistor device, comprising:

• a substrate;
• an epitaxial layer disposed over the substrate and comprising a source region and a drain region separated by a channel region along a first direction, wherein the epitaxial layer has an upper surface that is higher at a center than at rounded outer edges;
• a gate dielectric layer disposed over the epitaxial layer;
• and
• a conductive gate electrode disposed over the gate dielectric layer.

A transistor device, comprising:

• a silicon epitaxial layer disposed over a silicon substrate between a source region and a drain region separated along a first direction, wherein the silicon epitaxial layer has an upper surface that is higher at a center than at rounded outer edges;
• a gate dielectric layer arranged onto the silicon epitaxial layer, wherein the gate dielectric layer curves towards the silicon substrate along outer edges of the gate dielectric layer;
• and
• a conductive gate electrode disposed over the gate dielectric layer.