Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure

A method of manufacturing a split gate flash memory cell, said method comprising:

• forming a select gate on a semiconductor substrate;
• forming a sacrificial spacer laterally adjacent to the select gate and on a first side of the select gate;
• forming a charge trapping layer lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate;
• forming a memory gate over the charge trapping layer and on the second side of the select gate;
• and
• removing the sacrificial spacer.

An integrated circuit (IC) comprising:

• a select gate, a memory gate, and a sidewall structure laterally spaced over a semiconductor substrate with the select gate between the memory gate and the sidewall structure;
• a dielectric layer arranged between neighboring sidewalls of the select gate and the sidewall structure, and arranged under the sidewall structure;
• and
• a charge trapping layer arranged between neighboring sidewalls of the select gate and the memory gate, and arranged under the memory gate.