Semiconductor device and method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDoo-Young LEE, Sang-Hyun LEE, Myung-Hoon JUNG, Do-Hyoung KIM
Life of this patent
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Abstract
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.
Claims21
A semiconductor device comprising:
- a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height;
- an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns;
- a spacer contacting at least a portion of a sidewall of the insulating pattern defining the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights;
- and
- a contact structure filling the trench.
A semiconductor device comprising:
- a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height;
- an insulating pattern on the substrate, the insulating pattern covering the first and second gate patterns;
- an upper contact pattern between the first and second gate patterns, the upper contact pattern having a first width;
- a lower contact pattern on a lower portion of the upper contact pattern between the first and second gate patterns, the lower contact pattern having a second width narrower than the first width;
- and
- a spacer contacting a sidewall of the lower contact pattern, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights.
A semiconductor device comprising:
- a first spacer contacting a sidewall of a gate electrode, the first spacer having a first height;
- an insulating pattern contacting a sidewall of the first spacer;
- a second spacer contacting a sidewall of the insulating pattern, the second spacer different from the first spacer and having a second height greater than the first height, the first spacer, the insulating pattern, and the second spacer being sequentially arranged;
- and
- a conductive layer pattern contacting a sidewall of the second spacer.
21-25. (canceled)
Dependencies are inferred from the claim text.