Method to define the active region of a transistor employing a group iii-v semiconductor material
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chih Chen, Jiun-Lei Jerry Yu, Yu-Syuan Lin, Yao-Chung Chang, King-Yuen Wong
Life of this patent
Estimating the term…
Abstract
A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.
Claims22
A group III-V transistor device comprising:
- a group III-V heterojunction arranged over or within a substrate;
- an inner drain electrode arranged over the group III-V heterojunction;
- a gate having a ring shape and arranged over the group III-V heterojunction around the inner drain electrode;
- an outer source electrode having a ring-shaped region arranged over the group III-V heterojunction around the gate;
- and
- a passivation layer arranged over the group III-V heterojunction, wherein the inner drain electrode, the outer source electrode, and the gate extend through the passivation layer towards the group III-V heterojunction.
(canceled)
A method for manufacturing a group III-V transistor device, said method comprising:
- forming an inner drain electrode and an outer source electrode over a group III-V heterojunction, wherein the outer source electrode has a ring-shaped region surrounding the inner drain electrode;
- forming a gate over the group III-V heterojunction around the inner drain electrode between the outer source electrode and the inner drain electrode, wherein the gate has a ring shape;
- forming a second inner drain electrode and a second outer source electrode over the group III-V heterojunction, wherein the second outer source electrode is ring-shaped and surrounds the second inner drain electrode;
- and
- forming a second gate over the group III-V heterojunction, around the second inner drain electrode, and between the second outer source electrode and the second inner drain electrode, wherein the second gate has a ring shape.
15-18. (canceled)
A pair of neighboring group III-V transistor devices, the pair comprising:
- first and second inner drain electrodes arranged over a group III-V heterojunction;
- first and second gates corresponding to the first and second inner drain electrodes, wherein the first and second gates have a ring shape and are arranged over the group III-V heterojunction around the corresponding inner drain electrodes;
- first and second outer source electrodes corresponding to the first and second gates, wherein the first and second outer source electrodes each has an individual ring shape, wherein the individual ring shapes of the first and second outer source electrodes are merged together, and wherein the first and second outer source electrodes are arranged over the group III-V heterojunction and around the corresponding gates;
- a first active region arranged below the first gate, between the first inner drain electrode and the first outer source electrode;
- a second active region arranged below the second gate, between the second inner drain electrode and the second outer source electrode;
- and
- a group III-V region including the group III-V heterojunction and extending continuously between the first and second active regions without implant or etching isolation.
Dependencies are inferred from the claim text.