Method and Structure for III-V FinFET

A method for fabricating a semiconductor device, comprising:

• forming an insulator layer on a base layer, the insulator layer and the base layer defining a silicon-on-insulator substrate;
• forming a layer of III-V compound semiconductor material on the insulator layer;
• forming a plurality of fins in the layer of III-V compound semiconductor material;
• forming a semiconductor extension on each fin of the plurality of fins, each semiconductor extension comprising a III-V compound semiconductor material that is different from the III-V compound semiconductor material from which the plurality of fins is formed;
• forming at least one dummy gate structure across and perpendicular to the plurality of fins, each dummy gate structure comprising spacers on opposing sides thereof;
• forming a source/drain layer adjacent to the spacers on opposing sides of the at least one dummy gate structure;
• planarizing the source/drain layer;
• removing the at least one dummy gate structure to form a cavity and expose a portion of the semiconductor extension on the fin;
• removing the exposed portion of the semiconductor extension from the fin;
• etching the semiconductor extension to undercut the spacer;
• and
• forming a replacement gate structure in the cavity.

An apparatus for a semiconductor device, comprising:

• a substrate comprising a III-V compound semiconductor material;
• a plurality of fins formed in the III-V compound semiconductor material;
• a semiconductor extension on each of the fins, the semiconductor extensions each comprising a III-V compound semiconductor material that is different from a material forming the fins;
• a gate structure and a spacer across and perpendicular to the fins;
• a source/drain layer on a top surface of the substrate;
• and
• a planarization layer on a top surface of the source/drain layer;
• wherein the semiconductor extensions on each of the fins are etched from under the spacer to provide undercut regions beneath the spacer to expose a topmost surface of each fin to extend the gate/fin junction profile.