Bottom recess process for an outer blocking dielectric layer inside a memory opening

A method of fabricating a memory device, comprising:

• forming a stack including an alternating plurality of material layers and insulator layers over a substrate;
• forming a memory opening extending through the stack;
• forming a first blocking dielectric layer in the memory opening and over the stack;
• forming a sacrificial liner over the first blocking dielectric layer;
• forming an opening through a horizontal portion of the sacrificial liner;
• etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;
• removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed;
• forming a second blocking dielectric layer on the first blocking dielectric layer after removal of the sacrificial liner;
• and
• forming a memory material layer and a tunneling dielectric layer within the memory opening.

A method of fabricating a memory device, comprising:

• forming a stack including an alternating plurality of material layers and insulator layers over a substrate;
• forming a memory opening extending through the stack;
• forming a first blocking dielectric layer in the memory opening and over the stack, wherein the first blocking dielectric layer comprises aluminum oxide;
• forming a sacrificial liner over the first blocking dielectric layer, wherein the sacrificial liner comprises silicon oxide, silicon nitride or silicon, and the first blocking dielectric layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9;
• forming an opening through a horizontal portion of the sacrificial liner;
• etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;
• removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed;
• forming a second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner or after removing the sacrificial liner, wherein the sacrificial liner comprises silicon nitride or amorphous silicon;
• and
• forming a memory material layer and a tunneling dielectric layer within the memory opening.