Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
AssigneeSanDisk Technologies LLC
InventorsLiang PANG, Jayavel PACHAMUTHU, Yingda DONG
Life of this patent
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Abstract
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.
Claims31
A monolithic three-dimensional memory structure, comprising:
- a stack including an alternating plurality of insulator layers and electrically conductive layers located over a substrate;
- a memory opening extending through the stack;
- a memory film and a semiconductor channel located within the memory opening, wherein the semiconductor channel includes a vertical portion that extends vertically through a subset of layers within the stack;
- a drain region having a same horizontal cross-sectional area as the vertical portion of the semiconductor channel, wherein the drain region includes an electrical dopant of a first conductivity type.
A method of manufacturing a three-dimensional memory structure, comprising:
- forming a stack of alternating layers comprising first material layers and second material layers over a substrate;
- forming a temporary material layer over the stack;
- forming a memory opening through the temporary material layer and the stack;
- forming a memory film and a semiconductor channel in the memory opening;
- forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess;
- and
- introducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region.
Dependencies are inferred from the claim text.