Vertical nand device containing peripheral devices on epitaxial semiconductor pedestal

A method of fabricating a multilevel structure, comprising:

• forming a stack including an alternating plurality of material layers and insulator layers over a semiconductor substrate;
• forming an opening through the stack, wherein a top surface of the semiconductor substrate is exposed at a bottom of the opening;
• forming, within the opening, an epitaxial semiconductor pedestal in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate;
• forming an array of memory openings through the stack after formation of the epitaxial semiconductor pedestal;
• and
• forming an array of memory stack structures within the array of memory openings.

A three-dimensional NAND device, comprising:

• a stack of an alternating plurality of word lines and insulating layers located over a semiconductor substrate, each of the word lines and insulating layers being located at different levels that are vertically spaced from a top surface of the semiconductor substrate by different distances;
• an epitaxial semiconductor pedestal in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and having a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack;
• and
• an array of memory stack structures embedded within the stack,
• wherein each memory stack structure comprises:
• a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to the top surface of the semiconductor substrate through the stack;
• and
• at least one charge storage region located adjacent to the semiconductor channel.