US 2016/0111434 A1Published application

Three dimensional nand string memory devices and methods of fabrication thereof

AssigneeSanDisk Technologies LLC

InventorsJayavel PACHAMUTHU, Johann ALSMEIER, Henry CHIEN

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Abstract

Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.

Claims28

Dependent claims

A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material different than the first material over a substrate;
etching the stack to form a front side opening in the stack having a sidewall defined at least partially by the alternating layers of the first material and the second material;
removing a first portion of the second material layers through the front side opening to form front side recesses between the first material layers;
forming an amorphous or polycrystalline semiconductor material over at least a portion of the sidewall of the front side opening and within the front side recesses;
forming a layer of a metal material over at least a portion of the sidewall of the front side opening and adjacent to the amorphous or polycrystalline semiconductor material within the front side recesses;
annealing the metal material and the amorphous or polycrystalline semiconductor material within the front side recesses to form a large grain polycrystalline or single crystal semiconductor material charge storage region within each of the front side recesses by a metal induced crystallization process, wherein following the metal induced crystallization process at least a portion of the metal material is located between the charge storage regions and the second material layers;
forming a tunnel dielectric layer over the charge storage regions in the front side opening;
and
forming a semiconductor channel over the tunnel dielectric layer in the front side opening.

6 more elements

A monolithic three dimensional NAND memory device, comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;
a plurality of control gates extending substantially parallel to the major surface of the substrate, wherein each control gate comprises a first side surface facing the at least one end portion of the semiconductor channel, and the plurality of control gates comprise at least a first control gate located in a first device level and a second control gate located in a second device level located over the major surface of the substrate and below the first device level;
a plurality of vertically spaced apart charge storage regions, wherein each charge storage region comprises a first side surface facing a control gate and a second side surface facing the at least one end potion of the semiconductor channel, the charge storage regions comprising a single crystal or large grain polycrystalline semiconductor material and including at least one of a nickel and a nickel oxide residue located proximate to the first side surface of the charge storage region, and the plurality of vertically spaced apart charge storage regions comprise at least a first spaced apart charge storage region located in the first device level and a second spaced apart charge storage region located in the second device level;
a blocking dielectric located between the first side surface of the control gates and the first side surface of the charge storage regions;
and
a tunnel dielectric located between each one of the plurality of the vertically spaced apart charge storage regions and the semiconductor channel.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/520,084Filed 21 Oct 2014
Published: 21 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND