Lc module layout arrangement for contact opening etch windows
AssigneeMacronix International Co., Ltd.
InventorChin Cheng Yang
Life of this patent
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Abstract
A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting layer pairs with adjacent pairs differing in height by no more than the thickness of two insulating/conducting layer pairs.
Claims20
A three-dimensional semiconductor memory structure comprising:
- a plurality of LC modules, the modules comprising:
- contact pads;
- and
- layer-by-layer openings enabling connection with the contact pads, wherein:
- the LC modules are disposed on a plurality of levels, each level being formed from one or more pairs of alternating layers of conducting material and insulating material (OP layer pairs), wherein a height difference between surfaces of adjacent levels does not exceed a thickness of two OP layer pairs.
A method of forming a plurality of LC modules for a three-dimensional semiconductor memory comprising:
- providing a semiconductor stack formed on a substrate, the stack including a base layer and alternating conducting/insulating layers (OP layer pairs);
- defining a plurality of etch positions;
- performing a sequence of etches on the semiconductor stack to expose surfaces of OP layer pairs surfaces at the etch positions such that no adjacent surfaces differ in height by a thickness greater than a thickness of two OP layer pairs.
An apparatus comprising alternating pairs of layers of insulating material and conducting material configured to form a plurality of LC modules of a three-dimensional semiconductor memory array wherein:
- the alternating layers form distinct surfaces;
- and
- no two adjacent surfaces differ in height by an amount greater than a thickness of two pairs of conducting/insulating layers.
Dependencies are inferred from the claim text.