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US 2016/0111428 A1Published application
Semiconductor device and method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJu-Youn Kim, Hyung-Soon Jang, Jong-Mil Youn, Tae-Won Ha
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Abstract
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.
Claims30
A semiconductor device comprising:
- a substrate including a first active region, a second active region and a field region, the field region being disposed between the first active region and the second active region, the field region directly contacting both the first active region and the second active region;
- an interlayer dielectric layer disposed on or above the substrate and including a trench, the interlayer dielectric layer extending from the first active region to second active region;
- a gate dielectric layer disposed in the trench, and formed along sidewalls and a bottom surface of the trench;
- a first metal gate electrode disposed on or above the first active region, and disposed on a first sidewall and a bottom surface of the gate dielectric layer;
- and
- a second metal gate electrode disposed on or above the second active region, and disposed on a second sidewall and the bottom surface of the gate dielectric layer,
- wherein a contact surface between the first metal gate electrode and the second metal gate electrode is closer to the first active region than to the second active region, and
- a top surface of the first metal gate electrode, a top surface of the second metal gate electrode and a top surface of the interlayer dielectric layer are coplanar with each other.
5 more elements
A semiconductor device comprising:
- a substrate including a first active region, a second active region and a field region, the field region being disposed between the first active region and the second active region, the field region directly contacting both the first active region and the second active region;
- an interlayer dielectric layer disposed on or above the substrate and including a trench, the interlayer dielectric layer extending from the first active region to second active region;
- a gate dielectric layer disposed in the trench and including a high-k material, the gate dielectric layer including a first side portion formed on a first sidewall of the trench, a second side portion formed on a second sidewall of the trench and a bottom portion formed on a bottom surface of the trench;
- a gate structure disposed on or above the gate dielectric layer, the gate structure crossing the first active region, the second active region and the field region, the gate structure including a first metal gate electrode and a second metal gate electrode, the first metal gate electrode directly contacting the second metal gate electrode;
- and
- a layer disposed between the gate structure and the interlayer dielectric layer,
- wherein a top surface of the layer disposed between the gate structure and the interlayer dielectric layer is coplanar with a top surface of the gate structure and a top surface of the interlayer dielectric layer,
- the first metal gate electrode is disposed on or above the first active region,
- the second metal gate electrode is disposed on or above the second active region, and
- a contact surface between the first metal gate electrode and the second metal gate electrode is closer to the first active region than to the second active region.
7 more elements
A semiconductor device comprising:
- a substrate including a first active region, a second active region and a field region, the field region being disposed between the first active region and the second active region, the field region directly contacting both the first active region and the second active region;
- an interlayer dielectric layer disposed on or above the substrate and including a trench, the interlayer dielectric layer extending from the first active region to second active region;
- a gate dielectric layer disposed in the trench and including a high-k material, the gate dielectric layer including a first side portion formed on a first sidewall of the trench, a second side portion formed on a second sidewall of the trench and a bottom portion formed on a bottom surface of the trench;
- a first metal gate electrode disposed on or above the first active region, and disposed on or above the gate dielectric layer;
- and
- a second metal gate electrode disposed on or above the second active region, and disposed on or above the gate dielectric layer;
- a first spacer disposed between the first metal gate electrode and the interlayer dielectric layer;
- and
- a second spacer disposed between the second metal gate electrode and the interlayer dielectric layer,
- wherein the first metal gate electrode is disposed on or above the first active region,
- the second metal gate electrode is disposed on or above the second active region,
- a top surface of the first spacer is coplanar with a top surface of the first metal gate electrode,
- a top surface of the second spacer is coplanar with a top surface of the second metal gate electrode,
- the top surface of the first metal gate electrode, the top surface of the second metal gate electrode and a top surface of the interlayer dielectric layer are coplanar with each other, and
- a contact surface between the first metal gate electrode and the second metal gate electrode is closer to the first active region than to the second active region.
12 more elements
A semiconductor device comprising:
- a substrate including a PMOS forming region, an NMOS forming region and a field region, the field region being disposed between the PMOS forming region and the NMOS forming region;
- an interlayer dielectric layer disposed on or above the substrate and including a trench;
- a gate dielectric layer disposed in the trench;
- a p-type metal gate electrode disposed on or above the PMOS forming region, and disposed on or above the gate dielectric layer;
- and
- an n-type metal gate electrode disposed on or above the NMOS forming region, and disposed on or above the gate dielectric layer,
- wherein a top surface of the p-type metal gate electrode, a top surface of the n-type metal gate electrode and a top surface of the interlayer dielectric layer are coplanar with each other.
4 more elements
Dependencies are inferred from the claim text.