Semiconductor structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHUANG-KUI CHEN
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Abstract
The present disclosure provides a semiconductor structure includes a semiconductor layer having a first and a second surface, and an interlayer dielectric (ILD) defining a first metal gate and a second metal gate over the first and second surface, respectively. The first and second metal gate include a first SAC hard mask and a second SAC hard mask, respectively, wherein the first the second SAC hard mask have opposite stress to channel regions underneath the first and second metal gate, respectively. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming metal gate recesses, forming metal gates and SAC hard masks in the metal gate recesses, respectively.
Claims20
A semiconductor structure, comprising:
- a semiconductor substrate comprising a first and a second surface;
- an interlayer dielectric (ILD) with a first recess over the first surface of the semiconductor substrate and a second recess over the second surface of the semiconductor substrate;
- a first spacer lining a sidewall of the first recess, and a second spacer lining a sidewall of the second recess;
- a first high-k dielectric layer contacting a bottom of the first recess and a sidewall of the first spacer, and a second high-k dielectric layer contacting a bottom of the second recess and a sidewall of the second spacer;
- a first metal contacting bottom and sidewall of the first high-k dielectric layer, and a second metal contacting bottom and sidewall of the second high-k dielectric layer;
- wherein the first metal and the second metal are used for different conductive type semiconductor to each other;
- and
- a first SAC (Self-Aligned-Contact) hard mask on the first metal, and a second SAC hard mask on the second metal,
- wherein the first SAC hard mask and the second SAC hard mask have opposite stresses to channel regions underneath the first metal and the second metal.
A semiconductor structure, comprising:
- a semiconductor substrate comprising a surface;
- an interlayer dielectric (ILD) with a recess over the surface of the semiconductor substrate;
- a first spacer lining a sidewall of the recess;
- a source/drain region in the semiconductor substrate, adjacent to a channel region under the recess;
- a high-k dielectric layer contacting a bottom of the recess and a sidewall of the spacer;
- a metal contacting bottom and sidewall of the high-k dielectric layer;
- and
- a SAC hard mask on the metal,
- wherein the SAC hard mask has a tapered shape.
A method for manufacturing a semiconductor structure, comprising:
- forming a first and a second recess in an interlayer dielectric (ILD);
- forming a first spacer lining a sidewall of the first recess and a second spacer lining a sidewall of the second recess;
- forming a first high-k dielectric layer contacting a bottom of the first recess and a sidewall of the first spacer;
- forming a first metal contacting bottom and sidewall of the first high-k dielectric layer;
- forming a second high-k dielectric layer contacting a bottom of the second recess and a sidewall of the second spacer;
- forming a second metal contacting bottom and sidewall of the second high-k dielectric layer;
- and
- forming a first SAC hard mask on the first metal and a second SAC hard mask on the second metal;
- wherein the first SAC hard mask and the second SAC hard mask have opposite stresses to channel regions underneath the first metal and the second metal.
Dependencies are inferred from the claim text.