Multi-Voltage Complementary Metal Oxide Semiconductor Integrated Circuits Based On Always-On N-Well Architecture

A multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising:

• a plurality of first CMOS cells, each of the plurality of first CMOS cells having a supply terminal configured to receive a local supply voltage and a N-well (NW) terminal configured to receive a global supply voltage different than the local supply voltage;
• a plurality of second CMOS cells, each of the plurality of second CMOS cells having a supply terminal configured to receive the global supply voltage and a NW terminal configured to receive the global supply voltage, the second CMOS cells comprising always-on (AON) cells;
• one or more N-wells;
• and
• one or more always-on taps (ATAPs),
• wherein the NW terminal of at least one of the plurality of second CMOS cells and the NW terminal of at least one of the plurality of first CMOS cells comprise a first N-well of the one or more N-wells, and
• wherein the first N-well is configured to receive the global supply voltage through the one or more ATAPs disposed in the first N-well.