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US 2016/0111423 A1Published application
Extreme high mobility cmos logic
AssigneeIntel Corporation
InventorsSuman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar AmIan, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
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Abstract
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
Claims18
A transistor, comprising:
- a doped silicon semi-insulating substrate;
- a buffer layer disposed above the doped silicon semi-insulating substrate;
- a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;
- a group III-V material quantum well layer disposed above the bottom barrier layer;
- a top barrier layer disposed above the group III-V material quantum well layer;
- a gate stack disposed above the top barrier layer, the gate stack comprising:
- a high-k gate dielectric layer disposed above the top barrier layer;
- and
- a metal gate electrode disposed above the high-k gate dielectric layer;
- and
- raised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack.
8 more elements
A method of fabricating a transistor, the method comprising:
- forming a doped silicon semi-insulating substrate;
- forming a buffer layer above the doped silicon semi-insulating substrate;
- forming a bottom barrier layer above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;
- forming a group III-V material quantum well layer above the bottom barrier layer;
- forming a top barrier layer above the group III-V material quantum well layer;
- forming raised source and drain regions disposed above an etch stop layer formed above the top barrier layer;
- subsequent to forming the raised source and drain regions, forming a gate stack above the top barrier layer, forming the gate stack comprising:
- forming a high-k gate dielectric layer above the top barrier layer;
- and
- forming a metal gate electrode above the high-k gate dielectric layer, wherein the raised source and drain regions are on either side of the gate stack.
7 more elements
Dependencies are inferred from the claim text.