Method for making high voltage integrated circuit devices in a fin-type process and resulting devices

A device comprising:

• first and second pluralities of silicon fins on an upper surface of a substrate layer, separated by a space, wherein each pair of adjacent silicon fins is separated by a trench along the upper surface of the substrate layer;
• an oxide layer on the upper surface of the substrate layer filling in a portion of each trench along the upper surface of the substrate layer;
• first and second deep isolation trenches in the oxide layer and in the substrate layer adjacent to the first and second pluralities of silicon fins;
• a graded voltage junction comprising one or more concentration levels of a dopant in the substrate layer below each of the first and second pluralities of silicon fins;
• a gate structure on an upper surface of the oxide layer, positioned at the space between the first and second pluralities of silicon fins;
• source and drain regions implanted by a dopant in and under the first and second pluralities of silicon fins;
• and
• an epitaxial layer on the first and second pluralities of silicon fins forming merged source and drain fins, respectively.